1. Field of the Invention
The present invention is directed to a semiconductor device, particularly to the structure of an Integrated Injection Logic (to be called hereinafter as I.sup.2 L) device provided with a resistor element.
2. Description of the Prior Art
As is generally known in the art to which this invention pertains, Metal Oxide Semiconductor (MOS) integrated circuits and bipolar integrated circuits are mainly used to make up semiconductor digital logic circuits. Bipolar integrated circuits have complex structures and have a limited packing density, but have a comparatively high switching speed. These disadvantages of bipolar integrated circuits are compensated for in an I.sup.2 L device which has a relatively simple structure and a high function density and which consumes much less electric power.
A typical general purpose, n-p-n, planar, monolithic bipolar transistor is fabricated in an epitaxial n-type layer grown on an n.sup.+ buried layer supported by a p-type substrate, and is electrically isolated from other components in the layer by p-type diffusions through the epitaxial layer to the substrate. This isolation of epitaxial n-type layer by means of p-type diffusion is essential to fabricate a bipolar transistor. In this regard, an I.sup.2 L device can be fabricated without such p-type diffusion, which means a more simplified manufacturing process. This is why an I.sup.2 L device can compete with MOS integrated circuits.
A typical I.sup.2 L device is shown in cross-section in FIG. 1A. An epitaxial n-type layer is supported by an n.sup.+ substrate, and p-type diffusion through the epitaxial layer forms a p.sup.+ region for an injector I and a base region. An n-type diffusion in the base region n.sup.+ regions for collectors C.sub.1 and C.sub.2. As will be understood from the drawing, an I.sup.2 L device is formed to have a vertical pn junction structure, and if an electrical voltage of the order of 5-6 volts is applied and the vertical pn junction is forwardly biased, an electric current flows downwardly through, and from, the p-type region. In other words, the p-type region is not isolated from the n-type region. Because of this, the diffused p-type region does not function properly as a resistor layer.
In order to overcome the problem just described above, it is generally practiced in the art to form a resistor layer of n-type in the p-type region which is formed simultaneously with the formation of a base region. FIG. 1B illustrates in cross-section a resistor layer formed in accordance with a conventional technique. An epitaxial n-type layer 2 is formed on an n.sup.+ type silicon substrate 1, and a p.sup.+ type region 3 is formed simultaneously with the formation of a base region. Then, an n.sup.+ type electrode connection 4 for a resistor layer is formed simultaneously with the formation of an emitter region. Thereafter, a window is opened through the region where a resistor layer is to be formed using an oxide film 6, and impurities such as phosphorus or arsenic are diffused by conventional ion implantation fabrication technologies through the window, and after a subsequent heat treatment is over, a resistor layer 5 is formed.
Formation of such a resistor layer presents some problems while overcoming the problem mentioned before. Firstly, the resistor layer must be formed in a diffused region which is formed simultaneously with the base region of high impurity concentration by diffusion of impurities of higher impurity concentration in the same manner as with the formation of the emitter region, with the result that the withstand voltage of the resistor layer is relatively low. On the other hand, when impedance is taken into consideration it is advantageous to provide an input resistance in the I.sup.2 L type semiconductor device, but in such case if an input is from a Transistor-Transistor Logic (TTL) circuit, an input resistor having a withstand voltage of several volts is required. This presents a problem in fabricating a resistor layer with such a high withstand voltage.
Secondly, a resistor layer of the depth of 0.2 .mu.m or less is separately formed by ion implantation of 1.times.10.sup.15 /cm.sup.2 dose after fabrication of the emitter region as described above in order to attain a high-value resistance of the order of 500-600.OMEGA./.quadrature.. Since heat treatment is carried out subsequent to ion implantation, the depth of the emitter region or the width of the base region already formed is changed. This affects the current gain factor hFE that has been previously determined, and it is difficult in this case to control this hFE to have a desired value.
Thirdly, after the resistor layer has been fabricated, the region where the resistor layer is located is not covered by an oxide film, and thus is exposed. In order to cover the region, an oxide film 7 is deposited by conventional chemical vapour deposition. Then, as shown in the drawing, the surface of the semiconductor device has a two tiered structure with a lower oxide layer 6 having a considerable amount of impurities of phosphorus, for example, adhering thereto due to diffusion of the emitter region and formation of the resistor layer, and an upper oxide film 7 deposited by chemical vapour deposition as described above with much less impurities adhering. In an etching operation for opening a window for the connection of the electrode, the lower oxide layer 6 is side etched as well, as shown in FIG. 2, because it is etched at a higher rate due to impurities. When an electrode of aluminum for example is formed in the emitter region through the window, the electrode is likely to be open where the lower oxide layer is side etched because of its poor coverage there.
Formation of the resistor layer according to this conventional technique thus involves a number of problems.